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datasheet buffer/clock driver icslv810 idt? / ics? buffer/clock driver 1 icslv810 rev h 051310 description the icslv810 is a low skew 1.5 v to 2.5 v, 1:10 fanout buffer. this device is specifically designed for data communications clock management. the large fanout from a single input line reduces loading on the input clock. the ttl level outputs reduce noise levels on the part. typical applications are clock and signal distribution. features ? packaged in 20-pin qsop/ssop ? split 1:10 fanout buffer ? maximum skew between outputs of different packages 0.75 ns ? max propagation delay of 3.8 ns ? operating voltage of 1.5 v to 2.5 v on bank a ? operating voltage of 1.5 v to 2.5 v on banks b and c ? advanced, low power, cmos process ? industrial temperature range -40 c to +85 c ? 3.3 v tolerant input when vdda=2.5 v ? pb (lead) free packaging block diagram clk 1 clk 2 clk 3 clk 4 clk 5 clk 6 clk 7 clk 8 clk 9 clk 10 vdda vddb clkin vddc
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 2 icslv810 rev h 051310 pin assignment pin descriptions 20 pin (150mil) ssop clkin gnd clk 1 vdda clk 2 gnd clk 3 clk 4 vdda gnd gnd gnd vddb vddc clk 5 clk 6 clk 7 clk 8 clk 9 clk 10 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pin number pin name pin type pin description 1 clkin input clock input. 2 gnd power connect to ground. 3 clk1 output clock output. 4 vdda power connect to +1.5 - +2.5 v. 5 clk2 output clock output. 6 gnd power connect to ground. 7 clk3 output clock output. 8 vdda power connect to +1.5 - +2.5 v. 9 clk4 output clock output. 10 gnd power connect to ground. 11 clk5 output clock output. 12 clk6 output clock output. 13 gnd power connect to ground. 14 clk7 output clock output. 15 vddc power connect to +1.5 - 2.5 v. 16 clk8 output clock output. 17 gnd power connect to ground. 18 clk9 output clock output. 19 clk10 output clock output. 20 vddb power connect to +1.5 - 2.5 v.
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 3 icslv810 rev h 051310 external components the icslv810 requires a minimum number of external components for proper operation. decoupling capacitors decoupling capacitors of 0.01f must be connected between vdd and gnd, as close to these pins as possible. for optimum device performance, the decoupling capacitors should be mounted on the component side of the pcb. avoid the use of vias in the decoupling circuit. series termination resistor when the pcb trace between the clock outputs and the loads are over 1 inch, series termination should be used. to series terminate a 50 ? trace (a commonly used trace impedance) place a 33 ? resistor in series with the clock line, as close to the clock output pin as possible. the nominal impedance of the clock output is 20 ? . pcb layout recommendations for optimum device performance and lowest output phase noise, the following guidelines should be observed. 1) the 0.01f decoupling capacitors should be mounted on the component side of the board as close to the vdd pins as possible. no vias should be used between the decoupling capacitors and vdd pins. the pcb trace to vdd pin should be kept as short as possible, as should the pcb trace to the ground via. 2) to minimize emi the 33 ? series termination resistor, if needed, should be placed close to the clock output. absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the icslv810. these ratings, which are standard values for ics commercially rated parts, are stress ratings only. functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for exte nded periods can affect product reliability. electrical parameters are guaranteed only over the recommended operating temperature range. recommended operation conditions item rating supply voltage, vdd max 7 v all inputs and outputs -0.5 v to vdda + 1.2 v ambient operating temperature -40 to +85 c storage temperature -65 to +150 c junction temperature 125 c soldering temperature 260 c parameter min. typ. max. units ambient operating temperature -40 +85 c power supply voltage (measured with respect to gnd), vdda 1.425 2.625 v power supply voltage (measured with respect to gnd), vddb 1.425 2.625 v power supply voltage (measured with respect to gnd), vddc 1.425 2.625 v
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 4 icslv810 rev h 051310 dc electrical characteri stics?clkin and bank a vdda = 2.5 v , ambient temperature -40 c to +85 c note1: this parameter is not tested, guaranteed by design. dc electrical characteristics?bank b vddb = 2.5 v , ambient temperature -40 c to +85 c, unless otherwise noted parameter symbol conditions min. typ. max. units operating voltage vdda 1.425 2.625 v quiescent power supply current idda no load f = 40 mhz 15 ma short circuit current i os clk 1 - 5 80 ma input high voltage, clkin v ih guaranteed logic level high 1.6 v input low voltage, clkin v il guaranteed logic level low 0.8 v output high voltage v oh vin = vih or vil i oh = -7 ma 1.8 v output low voltage v ol vin = vih or vil i ol = 12 ma 0.4 v input high current i ih vdd = max vin = 2.4 v 1 a input low current i il vdd = max vin = 0.5 v -1 a input high current i i vdd = max vin = vdd (max) 20 a input capacitance c in vin = 0v, note1 5 6.0 pf output capacitance c out v out = 0v, note1 5.5 8.0 pf parameter symbol conditions min. typ. max. units operating voltage vddb 1.425 2.625 v quiescent power supply current iddb vddb = 2.5 v no load f = 40 mhz 7ma vddb = 1.5 v no load f = 40 mhz 3ma short circuit current i os vddb = 1.5 v clk8-10 35 ma vddb = 2.5 v clk8-10 80 ma
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 5 icslv810 rev h 051310 note1: this parameter is not tested, guaranteed by design. dc electrical characteristics?bank c vddc = 2.5 v , ambient temperature -40 c to +85 c, unless otherwise noted output high voltage v oh vddb = 1.5 v vin = vih or vil i oh = -7 ma 1.1 v vddb = 2.5 v vin = vih or vil i oh = -7 ma 1.8 v output low voltage v ol vddb = 1.5 v vin = vih or vil i ol = 12 ma 0.42 v vddb = 2.5 v vin = vih or vil i ol = 12 ma 0.4 v input high current i ih vddb = max 1 a input low current i il vddb = max -1 a input high current i i vddb = max, vin = vdd (max) 20 a input capacitance c in vin = 0v, note1 5 6.0 pf output capacitance c out v out = 0v, note 1 5.5 8.0 pf parameter symbol conditions min. typ. max. units operating voltage vddc 1.425 2.625 v quiescent power supply current iddc vddc = 2.5 v no load f = 40 mhz 3ma vddc = 1.5 v no load f = 40 mhz 2ma short circuit current i os vddc = 1.5 v clk6-7 35 ma vddc = 2.5 v clk6-7 80 ma output high voltage v oh vddc = 1.5 v vin = vih or vil i oh = -7 ma 1.1 v vddc = 2.5 v vin = vih or vil i oh = -7 ma 1.8 v output low voltage v ol vddc = 1.5 v vin = vih or vil i ol = 12 ma 0.42 v vddc = 2.5 v vin = vih or vil i ol = 12 ma 0.4 v input high current i ih vddc = max 1 a input low current i il vddc = max -1 a parameter symbol conditions min. typ. max. units
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 6 icslv810 rev h 051310 note1: this parameter is not tested, guaranteed by design. ac electrical characteristics?bank a vdda = 2.5 v , ambient temperature -40 c to +85 c input high current i i vddc = max, vin = vdd (max) 20 a input capacitance c in vin = 0v, note1 5 6.0 pf output capacitance c out v out = 0v, note 1 5.5 8.0 pf parameter symbol conditions min. typ. max. units output skew: skew between outputs of same package t sk(0 ) cl = 3 pf, rl = 500 ? figure 3 -200 200 ps pulse skew: skew between opposite transitions of same output (t plh -t phl ) t sk(p) cl = 3 pf, rl = 500 ? figure 4 -200 200 ps propagation delay t plh / t phl cl = 3 pf, rl = 500 ? figure 2 1.5 2.6 3.5 ns part to part skew t sk(t) cl = 3 pf, rl = 500 ? figure 5 -650 650 ps output rise time 20% to 80% t r(o) cl = 3 pf, rl = 500 ? 0.8 ns output fall time 80% to 20% t f(o) cl = 3 pf, rl = 500 ? 0.8 ns additive jitter t j all outputs 50 ps duty cycle measured at vdd/2 dc cl = 3 pf, rl = 500 ? 45 55 % duty cycle, vdda=1.8v dc 40 50 60 % output frequency range 1 133 mhz parameter symbol conditions min. typ. max. units
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 7 icslv810 rev h 051310 ac electrical characteristics?bank b vddb = 2.5 v , ambient temperature -40 c to +85 c, unless otherwise noted parameter symbol conditions min. typ. max. units output skew: skew between outputs of same package t sk(0 )c l = 3 pf, r l = 500 ? figure 3 -200 200 ps pulse skew: skew between opposite transitions of same output (t plh -t phl ) t sk(p) c l = 3 pf, r l = 500 ? figure 4 -200 200 ps propagation delay t plh / t phl c l = 3 pf, r l = 500 ?, vddb = 1.5 v figure 2 5.5 ns c l = 3 pf, r l = 500 ?, vddb = 2.5 v figure 2 1.5 2.6 3.5 ns part to part skew c l = 3 pf, r l = 500 ? vddb = 1.5 v figure 5 -1 1 ns c l = 3 pf, r l = 500 ? vddb = 2.5 v figure 5 -650 650 ps output rise time 20% to 80% t r(o) c l = 3 pf, r l = 500 ? vddb = 1.5 v 1.0 ns c l = 3 pf, r l = 500 ? vddb = 2.5 v 0.8 ns output fall time 80% to 20% t f(o) c l = 3 pf, r l = 500 ? vddb = 1.5 v 1.0 ns c l = 3 pf, r l = 500 ? vddb = 2.5 v 0.8 ns additive jitter t j all outputs, vddb = 1.5 v 34 ps all outputs, vddb = 2.5 v 50 ps duty cycle measured at vdd/2 dc cl = 3 pf, rl = 500 ? 45 55 % duty cycle, vddb = 1.8v dc 40 50 60 % output frequency range 1 133 mhz
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 8 icslv810 rev h 051310 ac electrical characteristics?bank c vddc = 2.5 v , ambient temperature -40 c to +85 c, unless otherwise noted parameter symbol conditions min. typ. max. units output skew: skew between outputs of same package t sk(0 )c l = 3 pf, r l = 500 ? figure 3 -200 200 ps pulse skew: skew between opposite transitions of same output (t plh -t phl ) t sk(p) c l = 3 pf, r l = 500 ? figure 4 -200 200 ps propagation delay t plh / t phl c l = 3 pf, r l = 500 ?, vddc = 1.5 v figure 2 5.5 ns c l = 3 pf, r l = 500 ?, vddc = 2.5 v figure 2 1.5 2.6 3.5 ns part to part skew c l = 3 pf, r l = 500 ? vddc = 1.5 v figure 5 -1 1 ns c l = 3 pf, r l = 500 ? vddc = 2.5 v figure 5 -650 650 ps output rise time 20% to 80% t r(o) c l = 3 pf, r l = 500 ? vddc = 1.5 v 1.0 ns c l = 3 pf, r l = 500 ? vddc = 2.5 v 0.8 ns output fall time 80% to 20% t f(o) c l = 3 pf, r l = 500 ? vddc = 1.5 v 1.0 ns c l = 3 pf, r l = 500 ? vddc = 2.5 v 0.8 ns additive jitter t j all outputs, vddc = 1.5 v 34 ps all outputs, vddc = 2.5 v 50 ps duty cycle measured at vdd/2 dc cl = 3 pf, rl = 500 ? 45 55 % duty cycle, vddc=1.8v dc 40 50 60 % output frequency range 1 133 mhz
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 9 icslv810 rev h 051310 thermal characteristics for 20qsop thermal characteristics for 20soic parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 135 c/w ja 1 m/s air flow 93 c/w ja 3 m/s air flow 78 c/w thermal resistance junction to case jc 60 c/w parameter symbol conditions min. typ. max. units thermal resistance junction to ambient ja still air 83 c/w ja 1 m/s air flow 71 c/w ja 3 m/s air flow 58 c/w thermal resistance junction to case jc 46 c/w
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 10 icslv810 rev h 051310 t plh input output from output under test cl=3pf 500 ohm v oh v ol v ih v il t phl v oh v ol v oh v ol input output 1 output 2 t sk t sk t plh1 t phl1 t plh2 t phl2 figure 2. propagation delay ( t sk(o) =|t plh2 -t phl2 | or |t plh1 -t phl1 | ) figure 3. output skew figure 1. load circuit figure 4. pulse skew ( t sk(p) =| tplh ? tph| ) v oh v ol input output 1 t plh1 t phl1 v oh v oh input package 1 output package 2 output t sk t sk t plh1 t phl1 t plh2 t phl2 ( t sk(o) =|t plh2 -t phl2 | or |t plh1 -t phl1 | ) figure 5. part-to-part skew v ol v ol
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 11 icslv810 rev h 051310 package outline and package dimensions (20-pin qsop, 150 mil. body) package dimensions are kept current with jedec publication no. 95 index area 1 2 20 d e1 e seating plane a 1 a a 2 e - c - b .10 (.004) c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a 1.351.75.053.069 a1 0.10 0.25 .0040 .010 a2 -- 1.50 -- .059 b 0.20 0.30 0.008 0.012 c 0.180.25.007.010 d 8.558.75.337.344 e 5.806.20.228.244 e1 3.80 4.00 .150 .157 e 0.635 basic 0.025 basic l 0.401.27.016.050 0 8 0 8
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 12 icslv810 rev h 051310 package outline and package dimensions (20-pin ssop, 209 mil. body) package dimensions are kept current with jedec publication no. 95 ordering information note: eol for non-green parts to occur on 5/13/10 per pdn u-09-01 "lf" suffix to the part number are the pb -free configuration and are rohs compliant. while the information presented herein has been checked for both ac curacy and reliability, integrat ed device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are implied. this product is intended for us e in normal commercial applications. any ot her applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommen ded without additional pr ocessing by idt. i dt reserves the right to change any circuitry or specificat ions without notice. idt does not authorize or warrant any idt product for use in life suppor t devices or critical medical instruments. part / order number marking shipping packaging package temperature lv810rilf lv810rilf tubes 20-pin qsop -40 to +85 c lv810rilft lv810rilf tape and reel 20-pin qsop -40 to +85 c LV810FILF LV810FILF tubes 20-pin ssop -40 to +85 c LV810FILFt LV810FILF tape and reel 20-pin ssop -40 to +85 c index area 1 2 20 d e1 e seating plane a 1 a a 2 e - c - b .10 (.004) c c l *for reference only. cont rolling dimensions in mm. millimeters inches* symbol min max min max a ? 2.00 ? .079 a1 0.05 ? .002 ? a2 1.65 1.85 .065 .073 b 0.22 0.38 0.009 0.015 c 0.09 0.25 .0035 .010 d 6.907.50.271.295 e 7.408.20.291.323 e1 5.00 5.60 .197 .220 e 0.65 basic 0.0256 basic l 0.550.95.022.037 0 8 0 8
icslv810 buffer/clock driver fan out buffer idt? / ics? buffer/clock driver 13 icslv810 rev h 051310 revision history rev. originator date description of change a p.griffith 03/25/05 ne w device/datasheet. b p.griffith 05/02/05 released from preliminary to final; changed short circuit current parameter in 2.5 v dc char table to 80 ma; changed short circuit current parameter in 1.5 v dc char table to 35 ma c p.griffith 05/12/05 added bullet in ?features? for oper ating voltage of 2.5 v on ba nk a and specified that operating voltages of 1.5 and 2.5 v are on banks b and c; changed block diagram input and pin 1 from in to clkin; removed +1.5 v spec from pin 4 and pin 8 descriptions; added ?vdda + 1.2 v? to ?all inputs and outputs? se ction of absolute maximum ratings; added min and max values for banks a, b, and c ?power supply voltage? in recommended operating conditions; expanded dc electrical char tables in to include a separate table for banks a, b, and c; expanded ac electrical char tables in to include a separate table for banks a, b, and c; d p.griffith 06/21/05 added 209 mil 20-pin ssop package and ordering info. e k. beckmeyer 07/27/05 specified operating voltage on bank a from 1.5v to 2.5v; added figures 4 and 5 on page 10 to explain pulse skew and part-to-part skew; changed output frequency max specification to 133mhz in ac electrical char tables for banks a, b, and c; added duty cycle spec for vdd = 1.5v in ac electrical char tables for banks a, b, c; changed clk conditions in dc electrical char tables on banks b and c; removed soic package. f k. beckmeyer 10/13/05 added ?lf? packaging and ordering info to both ?r? and?f? packages. g 12/17/09 added eol note for non-gren parts. h 05/13/10 removed eol note and non-green orderables.
? 2006 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt and the idt logo are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names a nd marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa corporate headquarters integrated device technology, inc. www.idt.com for sales 800-345-7015 408-284-8200 fax: 408-284-2775 for tech support www.idt.com/go/clockhelp innovate with idt and accelerate your future netw orks. contact: www.idt.com icslv810 buffer/clock driver fan out buffer

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